Phase-locked loops (PLLs) circuits are used in a variety of electronic systems. A PLL can generate an oscillating output signal having a phase that is related to the phase of the oscillating input signal. As an example, a PLL may include a variable frequency oscillator and a phase detector (PD). The variable frequency oscillator generates a periodic signal, and the PD compares the phase of that signal with the phase of the input periodic signal, adjusting the oscillator output frequency and phase to keep the phases matched. When used for synchronizing signals, a PLL can track input frequency and keeps the input and output frequencies and phases the same. Moreover, when used for frequency synthesis, PLL can also generate a frequency that is a multiple of the input frequency. PLLs can be implemented by using analog or digital circuits that consist of four basic elements, namely, phase-detector, low-pass filter, variable frequency oscillator, and feedback path. Digital PLLs employ a time-to-digital converter, digital loop filter, digitally controlled oscillator circuits instead of a charge pump, analog filter and voltage/current controlled oscillator circuits.
For integrated circuits that do not have a digital core or processor, such as standalone voltage/current mode controlled switching regulator ICs, analog PLL is generally utilized to synchronize the switching frequency to external clock. These applications have wide switching frequency that can range from 100 kHz to 3 MHz or more. PLL is also employed in these systems to lock onto phase and frequency of the external input clock to achieve multi-phase operation, to eliminate beat frequency noise, and to ensure that power supply noise is kept of sensitive frequency bands. In such systems, solution size and die area (cost), settling time, tuning range are very important design parameters. The design of analog PLLs at low input frequencies results in increased size and settling time. For example, charge-pump based analog PLL's smaller settling time requires a wider loop bandwidth. However, when used for input frequencies 100 kHz or lower, PLL has to meet its stability requirement by limiting its bandwidth and increasing its filter component sizes. As a result, PLL die area grows considerably and PLL settling time gets longer due to larger loop filter components. As low-cost and smaller circuit solutions become more in demand, there is a need for alternative solutions to have a smaller die area and settling-time PLL.